This invention relates to semiconductor memory devices.
MOS memories formed of insulated gate field-effect transistors (MOS transistors) are classed into dynamic memories which are advantageous for high density integration and static memories which are comparatively free from timing restrictions and are suited for high speed operation.
With a recent trend for increasing memory capacity, there have been demands for higher integration density and operation speed of memories. Particularly, various methods have been proposed for reducing the data readout time or access time. In practice, there are various considerations given to the address decoder circuit, sense amplifier circuit, input/output circuit, etc., and particularly great importance is attached to the improvement of the sense amplifier.
FIG. 1 shows a semiconductor memory provided with a positive feedback sense amplifier. It comprises a matrix array of memory cells MC-11 to MC-MN, word lines W1 to WN each commonly connected to the memory cells in each row, pairs of data lines D0-1 and D1-1, D0-2 and D1-2, . . . , D0-M and D1-M each pair commonly connected to the memory cells in each column, a row decoder 2 connected to the word lines W1 to WN for selecting one of these word lines in response to an address signal from an address signal generator circuit (not shown) and a column decoder 4 connected to the data lines D0-1 to D0-M and D1-1 to D1-M for selecting one of these pairs of data lines. It further comprises a precharging circuit 6, which is connected to the data lines D0-1 to D0-M and D1-1 to D1-M for precharging the pairs of data lines to the same potential level every time when the address designating operation is started or ended, an input/output unit 8 connected through a pair of input/output lines 9-1 and 9-2 to the column decoder 4 and which functions to permit data transfer between the selected one of the memory cells MC-11 to MC-MN and an external circuit (not shown), sense amplifiers SA-1 to SA-M connected to the respective pairs of the data lines and a clock pulse generator 10 for supplying trigger clock pulses to these sense amplifiers SA-1 to SA-M.
In this semiconductor memory circuit, the readout operation is effected as follows. The precharging circuit 6 precharges all the data lines D0-1 to D0-M and D1-1 to D1-M to a predetermined potential level, for instance, at the time of the commencement of the readout operation. Subsequently, the row decoder 2 selects one of the word lines W1 to WN in response to an address signal from the address signal generator circuit (not shown) to permit data in the memory cells connected to the selected word line to be read out. Meanwhile, the column decoder 4 selects a pair of data lines in response to an address signal from the address signal generator circuit. The data read out from the memory cell connected to the selected word and data lines is amplified by the corresponding sense amplifier. At this time, the change of the potential difference between the pair of data lines selected for effecting the transfer of data from the addressed memory is comparatively slow since a parasitic load capacitance which is comparatively heavy with respect to the driving capacity of the memory cell is coupled to the data lines D0-1 to D0-M and D1-1 to D1-M. When a predetermined value is reached by the potential difference between the selected pair of data lines, the corresponding sense amplifier effects positive feedback of the data signal on this pair of data lines, that is, increases the potential difference between the data lines of this pair, in response to a clock pulse from the clock pulse generator 10, whereby the data signal from the addressed memory cell is amplified and transferred through the column decoder 4 and input/output unit 8 to an external circuit (not shown).
In this case, the timing with which to activate the sense amplifiers SA-1 to SA-M is important. The utmost effect of the positive feedback by the sense amplifier can be obtained if the sense amplifier is activated when a potential difference, to which the sense amplifier can respond, is produced between the pair of data lines. However, if the activation is caused before this timing, erroneous data readout is likely to result, while with the activation after this timing the effect of the positive feedback by the sense amplifier is reduced.
Generally, where the gate electrodes of the MOS transistors constituting the memory cells are formed of polycrystalline silicon, the word lines W are formed of polycrystalline silicon layers, and data lines D0 and D1 are formed of metal layers. This is done so because in the silicon gate type MOS memory metal layers can be used as lead layers perfectly independently of polycrystalline silicon layers, thus providing greater freedom of the wiring, and also because the density of integration can be increased by forming the word lines, which are connected to the gate electrodes of the MOS transistors used for forming the memory cells, of polycrystalline silicon. However, whereas the sheet resistance of the metal layer is sufficiently low, that of the polycrystalline silicon layer is considerably high, of the order of several ten .OMEGA./.quadrature., so that the time required for the charging and discharging through the load capacitance parasitic to the polycrystalline silicon layer greatly differs between a memory cell near the decoder 2 and one remote therefrom; that is, the row address period is longest for the memory cell most distant from the row decoder 2. On the other hand, the data lines D0 and D1 which are formed of the metal layer are held practically at a uniform potential, and the readout time is thus substantially the same for all the memory cells arranged on the same column.
While the propagation time of the row address signal propagating through the word line is an important factor for determining the timing at which to activate the sense amplifiers SA-1 to SA-M, in the semiconductor memory circuit of FIG. 1 the sense amplifiers SA-1 to SA-M are activated according to clock pulses produced from the clock pulse generator 10 independently of the propagation time of the row address signal, so that with variations in the propagation time of the row address signal the proper activation timing cannot be obtained.
In the prior art, it has also been in practice to use direct positive feedback type sense amplifiers which can directly effect positive feedback of data to the pair of data lines in response to the potential difference between the pair of data lines. With these direct positive feedback type sense amplifiers it is possible to obtain the optimum timing with which to activate the sense amplifiers comparatively readily compared to the case of the semiconductor memory circuit of FIG. 1. However, since these sense amplifiers are of the direct positive feedback type, the amplification degree is low compared to that of the sense amplifiers in the semiconductor memory circuit of FIG. 1 when they are activated with the optimum timing.
FIG. 2 shows a different prior art semiconductor memory circuit. It is different from the semiconductor memory circuit of FIG. 1, in which the sense amplifiers SA-1 to SA-M are each connected between the data lines of each pair, only in that a sense amplifier 12 is connected between the pair of input/output lines 9-1 and 9-2.
Again in the semiconductor memory circuit of FIG. 2, the sense amplifier 12 is activated in response to clock pulses from the clock pulse generator 10 without directly monitoring the propagation time of the row address signals transmitted through the word lines W1 to WN, so that with variations in the propagation time of the row address signal the proper activation timing cannot be obtained.